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1/17 ? semiconductor msm514102d/dl description the msm514102d/dl is a 4,194,304-word 1-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm514102d/dl achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal cmos process. the msm514102d/dl is available in a 26/20-pin plastic soj, 20- pin plastic zip, or 26/20-pin plastic tsop. the msm514102dl (the low-power version) is specially designed for lower-power applications. features ? 4,194,304-word 1-bit configuration ? single 5 v power supply, 10% tolerance ? input : ttl compatible, low input capacitance ? output : ttl compatible, 3-state ? refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (l-version) ? static column mode, read modify write capability ? cs before ras refresh, hidden refresh, ras -only refresh capability ? multi-bit test mode capability ? package options: 26/20-pin 300 mil plastic soj (soj26/20-p-300-1.27) (product : msm514102d/dl-xxsj) 20-pin 400 mil plastic zip (zip20-p-400-1.27) (product : msm514102d/dl-xxzs) 26/20-pin 300 mil plastic tsop (tsopii26/20-p-300-1.27-k) (product : msm514102d/dl-xxts-k) xx indicates speed rank. product family msm514102d/dl-80 80 ns 150 ns 110 ns 385 mw 495 mw 5.5 mw/ family access time (max.) cycle time (min.) standby (max.) power dissipation msm514102d/dl-60 t rac 60 ns 40 ns t aa 30 ns 20 ns t cac 15 ns msm514102d/dl-70 70 ns 130 ns 440 mw 35 ns 20 ns operating (max.) 1.1 mw (l-version) e2g0149-29-41 ? semiconductor msm514102d/dl 4,194,304-word 1-bit dynamic ram : static column mode type this version: apr. 1999
2/17 ? semiconductor msm514102d/dl pin configuration (top view) pin name function a0 - a10 address input ras row address strobe cs chip select input d in data input d out data output we write enable v cc power supply (5 v) v ss ground (0 v) nc no connection 3 4 5 9 10 11 12 13 ras nc a10 a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 cs nc a9 a8 a7 a6 a5 a4 2 we 25 d out 1 d in 26 v ss 3 5 7 11 13 15 17 19 d out d in ras a0 a2 v cc a5 a7 1 a9 9 nc 26/20-pin plastic soj 3 4 5 9 10 11 12 13 ras nc a10 a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 cs nc a9 a8 a7 a6 a5 a4 2 we 25 d out 1 d in 26 v ss 4 6 8 12 14 16 18 20 v ss we a10 a1 a3 a4 a6 a8 2 cs 10 nc 20-pin plastic zip 26/20-pin plastic tsop (k type)
3/17 ? semiconductor msm514102d/dl block diagram we timing generator timing generator column decoders write clock generator sense amplifiers i/o selector output buffer d out d in input buffer memory cells row address buffers on chip v bb generator v cc v ss internal address counter column address buffers refresh control clock a0 - a10 ras cs row de- coders word drivers 11 11 11 11
4/17 ? semiconductor msm514102d/dl electrical characteristics absolute maximum ratings recommended operating conditions capacitance *: ta = 25 c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t symbol i os p d * t opr t stg C1.0 to 7.0 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 5.0 0 typ. parameter 4.5 0 2.4 C1.0 min. 5.5 0 6.5 0.8 max. (ta = 0c to 70c) v unit v v v input capacitance (a0 - a10, d in ) input capacitance ( ras , cs , we ) output capacitance (d out ) c in1 symbol c in2 c out 6 7 7 max. pf unit pf pf parameter (v cc = 5 v 10%, ta = 25c, f = 1 mhz) typ.
5/17 ? semiconductor msm514102d/dl dc characteristics parameter symbol condition msm514102 d/dl-60 msm514102 d/dl-70 msm514102 d/dl-80 (v cc = 5 v 10%, ta = 0c to 70c) i oh = C5.0 ma output high voltage i ol = 4.2 ma output low voltage 0 v v i 6.5 v; all other pins not input leakage current under test = 0 v d out disable output leakage current 0 v v o 5.5 v ras , cs cycling, average power t rc = min. supply current (operating) ras , cs = v ih power supply ras , cs current (standby) ras cycling, average power cs = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cs = v il , current (standby) d out = enable average power cs before ras supply current ( cs before ras refresh) ras = v il , average power address cycling, supply current t sc = min. (static column mode) t rc = 125 m s, average power v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc9 i cc10 cs before ras , supply current t ras 1 m s (battery backup) 3 v cc C0.2 v min. 2.4 0 C10 C10 max. v cc 0.4 10 10 90 2 1 90 5 90 80 300 200 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 80 2 1 80 5 80 70 300 200 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 70 2 1 70 5 70 60 300 200 unit v v m a m a ma ma ma ma ma ma m a m a note 1, 2 1 1, 2 1 1, 2 1, 3 1, 4, 5 1, 5 ras cycling, notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cs = v ih . 4. v cc C 0.2 v v ih 6.5 v, C1.0 v v il 0.2 v. 5. l-version.
6/17 ? semiconductor msm514102d/dl ac characteristics (1/2) parameter random read or write cycle time (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 12, 13 msm514102 d/dl-70 read modify write cycle time static column mode cycle time static column mode read modify write cycle time access time from ras access time from cs access time from column address output low impedance time from cs transition time refresh period refresh period (l-version) ras precharge time ras pulse width (static column mode) ras hold time cs precharge time (static column mode) cs pulse width ras pulse width cs hold time cs to ras precharge time ras to cs delay time ras to column address delay time row address set-up time row address hold time column address set-up time column address hold time column address hold time from ras column address to ras lead time output enable time referenced to we note 4, 5, 6 4, 5 4, 6, 7 8 3 5 6 4 4 cs to data output buffer turn-off delay time symbol t rc t rwc t sc t srwc t rac t cac t aa t clz t off t t t ref t ref t rp t ras t rasc t rsh t cp t cs t csh t crp t rcd t rad t asr t rah t asc t cah t ar t ral t ow min. 130 155 40 70 0 0 3 50 70 70 20 10 20 70 5 20 15 0 10 0 15 85 35 max. 70 20 35 20 50 16 128 10,000 100,000 10,000 50 35 20 unit ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 150 175 45 80 0 0 3 60 80 80 20 10 20 80 5 20 15 0 10 0 15 95 40 max. 80 20 40 20 50 16 128 10,000 100,000 10,000 60 40 20 max. 60 15 30 15 50 16 128 10,000 100,000 10,000 45 30 15 min. 110 130 35 60 0 0 3 40 60 60 15 10 15 60 5 20 15 0 10 0 15 75 30 msm514102 d/dl-80 msm514102 d/dl-60 access time from last write 4, 7 t alw 65 ns 75 55 data output hold time referenced to column address data output hold time from we t aoh t woh 5 0 ns ns 5 0 5 0 column address hold time from ras (write cycle) t awr 55 ns 60 50 column address hold time from ras precharge t ah 10 ns 10 10
7/17 ? semiconductor msm514102d/dl ac characteristics (2/2) symbol parameter read command set-up time t rcs read command hold time t rch msm514102 d/dl-70 read command hold time referenced to ras write command set-up time write command hold time write command hold time from ras write command pulse width write command to ras lead time write command to cs lead time data-in set-up time t rrh t wcs t wch t wcr t wp t rwl t cwl t ds data-in hold time t dh data-in hold time from ras t dhr cs to we delay time t cwd column address to we delay time t awd ras to we delay time cs active delay time from ras precharge ras to cs set-up time ( cs before ras ) ras to cs hold time ( cs before ras ) we to ras precharge time ( cs before ras ) we hold time from ras ( cs before ras ) ras to we set-up time (test mode) ras to we hold time (test mode) t rwd t rpc t csr t chr t wrp t wrh t wts t wth (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 12, 13 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 0 0 0 0 10 50 10 20 20 0 15 55 20 35 70 10 5 10 10 10 10 10 max. min. 0 0 0 0 15 60 15 20 20 0 15 60 20 40 80 10 5 10 10 10 10 10 max. min. 0 0 0 0 10 45 10 15 15 0 15 50 15 30 60 10 5 10 10 10 10 10 max. msm514102 d/dl-80 msm514102 d/dl-60 note 9 9 10 10 10 10 11 11 column address hold time t ahlw ns 65 75 55 last write to column address delay time t lwad ns 20 30 20 35 20 25 7 write invalid time write command hold time (d out disable) t wi t wh ns ns 10 0 10 0 10 0 10
8/17 ? semiconductor msm514102d/dl notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cs before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 2 ttl loads and 100 pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. operating within the t lwad (max.) limit ensures that t alw (max.) can be met. t lwad (max.) is specified as a reference point only. if t lwad is greater than the specified t lwad (max.) limit, then the access time is controlled by t aa . 8. t off (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 9. t rch or t rrh must be satisfied for a read cycle. 10. t wcs , t cwd , t rwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.) and t awd 3 t awd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. these parameters are referenced to the cs leading edge in an early write cycle, and to the we leading edge in a read modify write cycle. 12. the test mode is initiated by performing a we and cs before ras refresh cycle. this mode is latched and remains in effect until the exit cycle is generated. the test mode specified in this data sheet is an 8-bit parallel test function. ra10, ca10 and ca0 are not used. in a read cycle, if all internal bits are equal, the data output pin will indicate a high level. if any internal bits are not equal, the data output pin will indicate a low level. the test mode is cleared and the memory device returned to its normal operating state by performing a ras -only refresh cycle or a cs before ras refresh cycle. 13. in a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. these parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.
9/17 ? semiconductor msm514102d/dl e2g0150-18-41u timing waveform read cycle write cycle (early write) t asr row column v ih v il address d in v ih v il v ih v il v ih v il v ih v il C C C C C C C C C C t crp t rc t rp t ras t cs t csh t rah t asc d out "h" or "l" open valid data t rcd t cah t dhr t ds t dh v oh v ol e e t awr t crp t rad t wcr t wcs t wh t wp ras cs we t rsh t asr row column valid data v ih v il address d out "h" or "l" v ih v il v ih v il v ih v il e e e e e e e e t crp t rc open t rac t aa t off t rch t rrh t crp t rp t ras t cs t rcd t rsh t csh t rad t rah t ar t cac t ral v oh v ol e e t ah t rcs t clz ras cs we
10/17 ? semiconductor msm514102d/dl t asr row column v ih v il address d in v ih v il v ih v il v ih v il v ih v il C C C C C C C C C C t crp t rwc t crp t rp t ras t cs t rcd t rad t rah t rwd t ral d out "h" or "l" valid data t dh t cwd t awd t rcs t wp t csh t cwl valid data open t rac t aa t off t cac t clz t rwl v oh v ol e e t cah t ds t woh ras cs we read modify write cycle static column mode read cycle t asr row column v ih v il ras we cs v ih v il v ih v il v ih v il C C C C C C C C t crp t rp t rasc t rah "h" or "l" column column t cs t cs t cp t rsh t ral t rcd t rcs t rch t rrh t rac t aa t rch v oh v ol e e t clz t off t off t sc t sc t ah t rcs t cac t aoh t aa t aa t clz t cac t rad t ar t csh address d out valid data valid data valid data
11/17 ? semiconductor msm514102d/dl static column mode write cycle (early write) static column mode read modify write cycle v ih v il ras we cs v ih v il v ih v il v ih v il C C C C C C C C t crp t rp t rasc t cp t rsh t rad v oh v ol C C v ih C C row column column column t ral t awr t cah t rah t asr t cah t wp t wh t asc t asc t wch t wi t wcs t dhr t ds t ds t ds t dh t dh t dh "h" or "l" t rcd t cah t asc t wcs valid data valid data t sc address d in open d out t cwl v il valid data v oh v ol e e v ih e e v il v ih v il e e we v ih v il C C v ih v il C C v ih "h" or "l" t rasc t rp t crp t cwd t cwl t rwl t ral t lwad t cah t awd t rcs t rah t asr t rad t srwc t rwd t wp t awd t rcd t ds t dh t cac t aa t rac t woh t aa t ow t alw t off t clz row column valid data valid data column valid data valid data v il ras cs C C address d in d out
12/17 ? semiconductor msm514102d/dl static column mode read/write mixed cycle ras -only refresh cycle v ih v il ras v ih v il C C C C t crp t rp t ras d out "h" or "l" v oh v ol C C t rpc row v ih v il e e open address t asr t rah t rc note: we = "h" or "l" cs t off v ih C C v il v ih v il C C v il C v ih v il C C "h" or "l" t rcd t cp t wcs t wcr t awd t wp t ds t dh t lwad t ds t dh t dhr t aa t cac t aoh t aa t woh t alw (read) (read/write) valid data invalid data valid data valid data valid data v oh v ol e e we ras v ih v il C C t rah t rad t awr t sc t cah row column column column address d in d out v ih e t asc t cs t asr cs
13/17 ? semiconductor msm514102d/dl cs before ras refresh cycle hidden refresh read cycle v ih v il ras v ih v il C C C C t rp t ras d out "h" or "l" v oh v ol C C t rpc v ih v il C C open we t rc t wrh t wrp t rpc t wrp t cp t csr t chr t off note : address = "h" or "l" t csr cs t asr row column v ih v il ras address we v ih v il v ih v il v ih v il C C C C C C C C t crp t rc t rp t ras t rcd t rsh t rah t ah t rad t ral d out "h" or "l" v oh v ol e e t rrh t rcs valid data t rac t aa t off t clz t crp t wrh t wrp t cac t ar cs t rc t ras t chr
14/17 ? semiconductor msm514102d/dl hidden refresh write cycle test mode initiate cycle t asr row column v ih v il ras address v ih v il v ih v il C C C C C C t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t chr t ras t wrh t wrp we d in v ih v il v ih v il C C C C d out "h" or "l" v oh v ol e e valid data t ds t dh t dhr t wh open t ar t rc t crp cs t rp t wcs v ih v il ras v ih v il C C C C t ras d out "h" or "l" v oh v ol C C v ih v il C C open we t rc t wth t rpc t wts t cp t csr t chr t off note: address, d in = "h" or "l" t rp cs
15/17 ? semiconductor msm514102d/dl (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj26/20-p-300-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.80 typ. mirror finish
16/17 ? semiconductor msm514102d/dl (unit : mm) zip20-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.50 typ. mirror finish
17/17 ? semiconductor msm514102d/dl (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tsop ii 26/20-p-300-1.27-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.38 typ. mirror finish
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents cotained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan e2y0002-29-11

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